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Geopolitics and the changing landscape of global value chains and competition in the global semiconductor industry: Rivalry and catch-up in chip manufacturing in East Asia
This paper examines the changing landscape of GVCs and competition in the global semiconductor industry in the context of new geopolitics featured by the United States implementing “chokepoint” measures to limit the rise of semiconductor manufacturing in China. Overall, the paper finds that these US measures, like the IRA and CHIPS act, will have important impacts on semiconductor GVCs, especially in three types of memory (HBM, DRAM and NAND) and logic chips, and will slow down the speed and process of China's catching up and possibility of leapfrogging. By developing a conceptual framework for analyzing realism-based great power rivalries and national firm responses, we note that lead firms in South Korea and Taiwan can muddle through by reconfiguring their modes of GVCs, which can be summarized as “a bigger capacity and higher-ends in home bases and a smaller capacity and lower-ends abroad.” Analyses of US patents show that Korea and Taiwan have maintained their technological superiority in terms of both quantity and quality of their patents, compared to China, whereas Japan has lost its past superiority to China at least in patent quantity. We also find that the pace of China's catch-up is very fast in quantity, but slow in quality in key segments (DRAM, NAND and logic chips), except HBM which is the most recent segment where China has already surpassed Korea or Taiwan in terms of the number of patents. Whereas China has been catching up rapidly in the number of patents, it might encounter problems in turning that into market catch-up given the existing restrictions in accessing complementary technologies and chipmaking equipment, such as advanced lithography machines (EUV) or even more matured technologies (DUV), and software. Severely constrained by these technological entry barriers, the degree of catching up by China tends to be faster in lower-end products by foundry firms (e.g. SMIC), medium to high in NAND memory chips (e.g. YTMC), and slow or difficult in DRAM (e.g. CXMT). In the meantime, China has been making progress in domesticating value chains in diverse equipment and components in chip manufacturing.
A novel jujube tree trunk and branch salient object detection method for catch-and-shake robotic visual perception
Visual perception has become a prerequisite for automated jujube harvesting robot operations under complex orchard conditions. Catch-and-Shake harvesting, as the most efficient and common harvesting method, has widely been applied on various manually operated harvesters to complete large-area jujube fruit harvesting. However, the main factors restricting the development of existing harvesters are labor shortage, high labor cost, and low operating efficiency. To address the issues, we designed a catch-and-shake harvesting robot for jujube tree trunks and branches visual perception that can provide a barrier-free catch-and-shake operation area and guide the manipulator to reach the area to complete the harvesting operation. Meanwhile, a visual perception system including tree trunks and branches detection, skeleton extraction, catch-and-shake area confirmation was presented to guide robot intelligent operations. In the visual perception system, a novel salientobjectdetectionmodel called feature intersection and fusion Transformer (FIT-Transformer) network was proposed to split branches and background to provide reference for determining safe catch-and-shake areas. Moreover, we designed a diverse feature aggregation (DFA) and an attention feature fusion module (AFFM) to strengthen feature learning capabilities and obtain robust perception models. Comparative experimental results showed that our proposed FIT-Transformer model outperformed 12 state-of-the-art (SOTA) algorithms including C2FNet, RAS, BASNet, U2Net, SCRNet, PiCANet, EDRNet, EGNet, ICONR, VST, TransSOD and ABiU_Net. Specifically, the segmentation accuracy of jujube tree trunks and branches using our method showed the satisfactory result on five evaluation indexes under natural environment (the EM, SM, WF, FM and MAE reached 0.9713, 0.8991, 0.8854, 0.8905, and 0.0302, respectively). Field experiments also proved that our method could meet the requirements of operational accuracy and real-time operations.
PaLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition
As the technology node scales down to 5nml3nm, the consequent difficulty has been widely lamented. The defects on the surface of wafers are much more prone to emerge during manufacturing than ever. What's worse, various single-type defect patterns may be coupled on a wafer and thus shape a mixed-type pattern. To improve yield during the design cycle, mixed-type wafer defect pattern recognition is required to perform to identify the failure mechanisms. Based on these issues, we revisit failure dies on wafer maps by treating them as point sets in two-dimensional space and propose a two-stage classification framework, PoLM. The challenge of noise reduction is considerably improved by first using an adaptive alpha-shapes algorithm to extract intricate geometric features of mixed-type patterns. Unlike sophisticated frameworks based on CNNs or Transformers, PoLM only completes classification within a point cloud cluster for aggregating and dispatching features. Furthermore, recognizing the remarkable success of large pre-trained foundation models (e.g., OpenAI's GPT-n series) in various visual tasks, this paper also introduces a training paradigm leveraging these pre-trained models and fine-tuning to improve the final recognition. Experiments demonstrate that our proposed framework significantly surpasses the state-of-the-art methodologies in classifying mixed-type wafer defect patterns.
Catch the Butterfly: Peeking into the Terms and Conflicts Among SPDX Licenses
The widespread adoption of third-party libraries (TPLs) in software development has significantly accelerated the creation of modern software. However, this convenience comes with potential legal risks. Developers may inadvertently violate the licenses of TPLs, leading to legal issues. While existing studies have explored software licenses and potential incompatibilities, these studies often focus on a limited set of licenses or rely on low-quality license data, which may affect their conclusions. To address this gap, there is an urgent need for a high-quality license dataset that encompasses a broad range of mainstream licenses and provides accurate terms and conflict information, to help developers navigate the complex landscape of software licenses, avoid potential legal pitfalls, and guide more informed and effective solutions for managing license compliance and compatibility in software development. To this end, we conduct the first work to understand the mainstream software licenses based on term granularity and obtain a high-quality dataset of 453 SPDX licenses with well-labeled terms and conflicts. Specifically, we first conduct a differential analysis of the mainstream platforms that provide license data to understand the terms and attitudes of each license. N ext, we further propose a standardized set of license terms to capture and label existing mainstream licenses with high quality. Moreover, we improve the existing license conflict mode to include copyleft conflicts and conclude the three major types of license conflicts among the 453 SPDX licenses. Based on the dataset, we carry out two empirical studies to reveal the concerns and threats from the perspectives of both licensors and licensees. One study provides an in-depth analysis of the similarities, differences, and conflicts among SPDX licenses, and the other revisits the usage and conflicts of licenses in the NPM ecosystem and draws conclusions that differ from previous work. Our studies reveal some insightful findings and disclose relevant analytical data, which set the stage for further research into the complexities of license compliance and compatibility.